In ATM switch, the order of cell discard when a large number of cells are input exceeding the switch's exchange capability, or the order of reading of cells accumulated in cell buffer is preset as a discard characteristic or a delay characteristic, and the cell transfer control in conducted according to the characteristic.
By properly conducting the discard order and the delay order (in other words, the order of reading from cell buffer), the quality of service can be guaranteed. The quality of service is represented by `QOS(quality of service)`.
As a prior art to the invention, for example, Japanese patent application laid-open No.7-297840 (1995) discloses `priority control system in output buffer type ATM switch` (hereinafter referred to as `prior art 1`). FIG. 1 is a block diagram showing the circuit composition of the ATM switch used in prior art 1.
An example of the conventional circuit composition and operation will be explained in FIG. 1.
In the example of FIG. 1, when a cell is transferred from N input ports HWIN-1 to -N to N output ports HWOUT-1 to -N, an input buffer 2 to each input port and an output buffer 12 to each output port are provided.
Each input buffer 2 in provided with one logical queue 22 for each output port and each service class QOS guaranty, a write controller 21 to control the writing into this logical queue 22, and a read controller 23 to control the reading of this logical queue 22.
A cell output from each input buffer 2 is connected through a switch 11 to an output buffer 12 corresponding to the addressed output port. To each output buffer 12, a cell threshold detector 13 to detect a congestion signal to indicate whether the amount of cells accumulated in the output buffer 12 exceeds a predetermined threshold value or not is connected. All the output signals of the detectors 13 are input to the read controller 23 of each input buffer 2.
In the system shown in FIG. 1, for each cell, a discard quality class and a delay quality class are predetermined. The read controller 23 temporarily changes the classes according to a signal from the cell threshold detector 13. After the changing, it controls the logical queues so that they are sequentially output in order of class height.
Meanwhile, when a large-scale switch is composed, designing a switch with large switch processing can minimize the size of hardware. Also, to get a good control characteristic, it is necessary to add QOS guaranty, i.e., control functions to guarantee mainly a discard characteristic and a delay characteristic. However, the more the control function is complicated, the longer the time of processing needs to be.
Also, when the switch has larger switch processing, time of processing to be assigned to one cell is reduced. Therefore, it becomes difficult to complicate the control function so as to guarantee QOS.
Further, when the output link band of switch is enlarged, a higher characteristic to the amount of buffers mounted can be obtained by the statistical multiplexing effect.
Therefore, it is desirable that ATM switches are comprised of multistage, e.g., two-stage, switch units, where the first-stage switch unit is so comprised that the size of switch processing is made as large as possible, the link band is increased, function as to QOS guaranty is simplified, and the second-stage switch unit is comprised of an assembly of small-scale and multifunctional switches to conduct the switch processing at output port band and to sufficiently achieve the function as to QOS guaranty.
However, if the second-stage switch unit is provided with all the function as to QOS guaranty, there will be no means for controlling the cell discard by HOL (head of line blocking) occurring in the first-stage switch unit. Therefore, the means for controlling the cell discard must be also given to the first-stage switch unit.
However, the first-stage switch unit must have such a low cell discard ratio that does not influence the cell discard control characteristic by QOS guaranty of the second-stage switch unit.
A problem for the circuit disclose din prior art 1 is that the input cell buffer 2 in FIG. 1 conducts the control as to QOS guaranty. Namely, the queuing management is necessary for service class unit to conduct QOS guaranty and for each output port unit. Therefore, the circuit size has to be enlarged as the number of management is increased.
Also, it is difficult to conduct the QOS guaranty at the input buffer 2 distant from the output port because it is to be conducted to the output port link band.